With the continuous development of integrated circuits, in order to save space, a variety of devices are manufactured on the same chip at the same time. For example, in a BCD (Bipolar-CMOS-DMOS) process, high voltage (HV) of the laterally diffused metal oxide semiconductor (LDMOS) and low voltage (LV) of the CMOS devices are integrated on the same chip. Referring to FIG. 1, a semiconductor substrate 100 includes LDMOS 110 and CMOS 120, which are separated by a filed oxide layer 114. The LDMOS 110 has a drift region 111 between the source region and the drain region. The low doped drift region can withstand a higher voltage due to its high impedance. As shown in FIG. 1, the gate 112 of the LDMOS extends to above the drift region oxide layer 113 of the drift region to be regarded as a field plate.
The LV CMOS employs a very thin gate oxide with a thickness of 100 to 200 angstroms, and the quality of the substrate surface determines the quality of the gate oxide. Before growing the gate oxide, the substrate surface must be oxidized, and the oxide layer is removed via etching, thus exposing a high quality gate oxide. This process is also known as the sacrificial oxidation process. Typically, to ensure the complete removal of the sacrificial oxide layer, the etching loss of the oxide layer is greater than the growth of the sacrificial oxide layer.
A manufacturing method for a semiconductor device according to a prior art is shown in FIG. 2 and FIG. 3, which includes:
Step S301, a semiconductor substrate 200 is provided, which includes a LDMOS region and a CMOS region.
Step S302, a masking layer 201 is formed on the semiconductor substrate.
Step S303, an LDMOS drift region 202 is formed using the masking layer 201 as a mask; and a drift region oxide layer 203 is formed on the drift region 202.
Step S304, the masking layer 201 is removed.
Step S305, a sacrificial oxide layer 204 is formed on the semiconductor substrate.
Step S306, the sacrificial oxide layer is removed.
Step S307, a gate oxide 211 and a gate 210 of the CMOS are formed on the semiconductor substrate 500 treated by the sacrificial oxidation. Then subsequent production processes are performed by diffusion, photolithography, etching, thin-film processing.
Referring to FIG. 2 and FIG. 3, since the step of sacrificial oxidation is configured after the step of forming drift region oxide layer, during the etching process of the sacrificial oxide layer, the drift region oxide layer of HV LDMOS is also etched. At a corner area 221 shown in FIG. 4 and FIG. 2G, the edge of the drift region oxide layer is susceptible to damage. In addition, the area shown in dashed lines in FIG. 2F is etched as the drift region oxide layer 203. Although the corner portion on edge of the drift region oxide layer will be oxidized to a certain extent during the process of forming the gate oxide, the oxide layer at the corners is too thin, which will cause breakdown of the LDMOS device due to the higher electric field across the drift region.
One solution in the prior art is to increase the length of the drift region to elevate the breakdown voltage. However, this method also has some problems.
LDMOS device is a single structure unit consisting of hundreds LDMOS units, and the more the number of units, the stronger the drive capability of the LDMOS device. The increased length of the drift region results in an increased area of the LDMOS unit chip, such that the number of unit is decreased, thereby decreasing the drive capability of the LDMOS device under the same area.
Furthermore, on-resistance is a resistance of a working device from drain to source, and when the on-resistance is small, a larger output current occurs, such that the device will be provided with a good switching characteristics and a more powerful drive capability. However, the increased length of the drift region results in an increased on-resistance, thereby further decreasing the drive capability of the LDMOS device.
Accordingly, increasing the length of the drift region to improve the breakdown voltage will increase the on-resistance and chip area, thus reducing the driving capability of the LDMOS device.
When implementing the manufacturing of the LDMOS device, the inventors has found that there are at least the following problems in the prior art:
The silicon on the edge of an oxide layer in an LDMOS drift region is easily exposed, which leads to leakage on the junction edge and causes breakdown of the LDMOS device.